Many electronic circuit designs today have strict requirements on device performance parameters such as switching performance and on-state resistance. Trench power Metal Oxide Semiconductor Field Effect Transistors (MOSFET) devices are often used in such circuits. Existing fabrication techniques for trench MOSFETs are typically complex and expensive, usually requiring 6 or more masks to be applied during processing.
FIG. 1 is a cross-sectional view of the conventional trench MOSFET device 100. As shown in FIG. 1, trenches 102 are formed in the semiconductor wafer 104 that includes a silicon substrate. By way of example, the silicon substrate may include an epitaxial (epi) layer 108 formed on a heavily doped bottom substrate layer (not shown). Body regions 106 are formed in a top portion of epi layer 108. Source regions 110 are formed on the top portion of the body regions 106. Gate electrodes 101 are formed in the trenches 102 by filling the trenches with polysilicon. The gate electrodes 101 are insulated from the silicon by an oxide layer 114. A metal 112 is formed on top of the wafer 104. In this device, the tops of gate electrodes 101 are recessed below a top surface of the source regions 110, which requires deep junctions, large source contact area (potentially smaller mesa) and the is not compatible with trench-contact (i.e., trench contact to source and body regions), due to alignment issues.
FIG. 2 is a cross-sectional view of another conventional trench MOSFET device 200. The structure of the device 200 is similar to the device 100, which includes trenches 202 formed in the semiconductor wafer 204 containing a silicon substrate. By way of example, the silicon substrate may include an epitaxial (epi) layer 208 formed on a heavily doped bottom substrate layer (not shown). Body regions 206 are formed in a top portion of epi layer 208. Source regions 210 are formed on the top portion of the body regions 206. Gate electrodes 201 formed in the trenches 202 are polysilicon stick up (PSU) type with oxide 214 for insulating from the silicon wafer 204. Adjacent to the tops of the PSU gate electrodes 201 are oxide spacers 207 formed on the top surface of the semiconductor wafer 204. A metal 212 is formed on top of the wafer 204. In this device, the gate electrodes 201 are extended above a top surface of the source regions 210. This type of device has shallow junctions, bigger cell pitch, e.g., about 0.2 micron to 0.3 micron because of the oxide spacers 207, but is trench-contact compatible. However, this raises process control issues, such as controlling the thickness and integrity of the thin oxide between the top corner of the gate electrode 201 and the metal 212.
FIG. 3 is a cross-sectional view of another conventional trench MOSFET device 300. As shown in FIG. 3, gate trench 302 and contact trench 303 are formed in a semiconductor wafer 304 containing a semiconductor substrate which may include an epitaxial (epi) layer 308 formed on a heavily doped bottom substrate layer (not shown). Body regions 306 are formed at a top portion of the epitaxial layer 308. Source regions 310 are formed at a top portion of the body regions 306. A metal 312 is formed on top of the wafer 304. The gate electrode 301 is insulated from the silicon wafer 304 and the metal 312 with an oxide layer 314. However, the gate trench 302 and the contact trench 303 are initially delineated in a single step using a same mask; therefore extra masks are used to protect contact or gate trench in subsequent processes to differentiate the contact trench and the gate trench. Such a process avoids alignment issues, but requires an extra mask compared to self-aligned methods of forming the contact trench. Such a process is disclosed in U.S. Pat. No. 7,767,526, as will be later explained. The disclosures of U.S. Pat. No. 7,767,526 are incorporated herein by reference.
U.S. Pat. No. 6,916,745 discloses a method of forming a trench MOSFET having self-aligned features comprising. In this method, a portion of the silicon layer is removed to form a middle section of a trench and the outer sections of the trench extending into the silicon layer from the exposed surface area of the silicon layer. The middle section of the trench is extending deeper into the silicon layer than the outer sections of the trench. A gate electrode is formed by filling the trench with polysilicon and etching back the polysilicon so that the polysilicon partially fills the trench to below the outer sections of the trench.
U.S. Pat. No. 5,801,417 discloses a recessed gate power MOSFET formed on a substrate including a P-body layer, N-drain layer and optional P+ layer for IGBT. First, a trenching protective layer formed on the substrate is patterned to define exposed areas as stripes or a matrix, and protected areas. Sidewall spacers of predetermined thickness with inner surfaces contact the protective layer sidewalls. A first trench is formed in substrate areas with sidewalls aligned to the sidewall spacer outer surfaces and extending depthwise through the P-body layer to at least a predetermined depth. Gate oxide is formed on the trench walls and gate polysilicon refills the trench to a level near substrate upper surface. Oxide between sidewall spacers covers polysilicon. Then the protective layer exposing upper substrate surface between spacer inner surfaces is removed. This area is doped to form a source layer atop the body layer and then trenched to form a second trench having sidewalls aligned to the spacer inner surfaces. Second trench defines vertically-oriented source and body layers stacked along gate oxide layer to form vertical channels on opposite sides of second trench. Source and body layers have a lateral thickness established by the predetermined spacing of the inner and outer surfaces of the sidewall spacers. Source conductor in the second trench contacts the N-source and P-body layers, and an enhanced P+ region at the base of the second trench.
U.S. Pat. No. 7,390,717 discloses a fabrication process for a trench type power semiconductor device includes forming inside spacers over a semiconductor surface. Using the spacers as masks, trenches with gates are formed in the semiconductor body. After removing the spacers, source implants are formed in the semiconductor body along the trench edges and are then driven. Insulation caps are then formed over the trenches. Outside spacers are next formed along the sides of the caps. Using these spacers as masks, the semiconductor surface is etched and high conductivity contact regions formed. The outside spacers are then removed and source and drain contacts formed. Alternatively, the source implants are not driven. Rather, prior to outside spacer formation a second source implant is performed. The outside spacers are then formed, portions of the second source implant etched, any remaining source implant driven, and the contact regions formed. The gate electrodes are either recessed below or extend above the semiconductor surface.
U.S. Pat. No. 7,767,526 of Alpha & Omega Semiconductor Incorporated discloses a fabrication process for trench gate MOSFET devices using composite masking, which includes a single mask to pre-define gate trenches and body contact trenches. First an initial hard mask layer (e.g. oxide) is formed and patterned on a surface of a semiconductor substrate for a single trench etch to predefine locations for a body contact trench and a gate trench. The predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth, with the other regions covered by a combination of the initial hard mask and the gate trench mask.
US patent publication number 20090242973 of Alpha & Omega Semiconductor, LTD discloses a method for manufacturing a vertical power MOSFET device using technique an oxide cap with a conductive polysilicon spacer. The method includes forming a trench with a predetermined depth in the N-epi layer, forming a gate electrode in the trench, implanting and diffusing dopants into a top region of the N-epi layer to form a P-body layer and source region, forming oxide on top of the gate electrode and the source region, etching portions of the oxide to expose selected portions of the source region, etching selected portions of the source region not covered by the oxide down to the p-body layer, and forming N+ doped polysilicon spacers disposed along the sidewalls of the remaining portions of the source region and the oxide. The N+ doped polysilicon spacers increase the contact area to the source region.
US patent publication number 20100032751 of ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED discloses a method for manufacturing a vertical power MOSFET device using technique of poly stick up (PSU) with spacers. The method includes forming a trench in the epitaxial layer (which may include a body region), forming a gate electrode in the trench with a gate oxide disposed between the gate electrode and the epitaxial layer, forming a cap insulator over the gate electrode and etching back around the cap insulator such that the top of the gate electrode is even with or protrudes above a surface of the epitaxial layer, forming a polysilicon spacer on the epitaxial layer self-aligned to the cap insulator, diffusing at least a portion of the dopants of the polysilicon spacer into the body layer to form a source region below the polysilicon spacer, and implanting a body contact region in the body, which is self-aligned to the polysilicon spacer.
It is within this context that embodiments of the present invention arise.